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LTC2224 12-Bit, 135Msps ADC
FEATURES

DESCRIPTIO
Sample Rate: 135Msps 67.3dB SNR up to 140MHz Input 80dB SFDR up to 150MHz Input 775MHz Full Power Bandwidth S/H Single 3.3V Supply Low Power Dissipation: 630mW CMOS Outputs Selectable Input Ranges: 0.5V or 1V No Missing Codes Optional Clock Duty Cycle Stabilizer Shutdown and Nap Modes Data Ready Output Clock Pin Compatible Family 135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit) 105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit) 80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit) 48-Pin 7mm x 7mm QFN Package
The LTC(R)2224 is a 135Msps, sampling 12-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2224 is perfect for demanding communications applications with AC performance that includes 67.3dB SNR and 80dB spurious free dynamic range for signals up to 150MHz. Ultralow jitter of 0.15psRMS allows undersampling of IF frequencies with excellent noise performance. DC specs include 0.4LSB INL (typ), 0.3LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.5LSBRMS. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V. The ENC+ and ENC - inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.
, LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
APPLICATIO S

Wireless and Wired Broadband Communication Cable Head-End Systems Power Amplifier Linearization Communications Test Equipment
TYPICAL APPLICATIO
REFH REFL FLEXIBLE REFERENCE
3.3V VDD 0.5V TO 3.6V OVDD
+
ANALOG INPUT INPUT S/H
-
12-BIT PIPELINED ADC CORE
CORRECTION LOGIC
OUTPUT DRIVERS
D11 * * * D0
SFDR (dBFS)
OGND CLOCK/DUTY CYCLE CONTROL
2224 TA01
ENCODE INPUT
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SFDR vs Input Frequency
95 90 4th OR HIGHER 85 80 75 70 65 60 55 50 0 100 200 300 400 500 INPUT FREQUENCY (MHz) 600 2nd OR 3rd
2224 TA01b
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LTC2224
ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO
TOP VIEW
48 GND 47 VDD 46 VDD 45 GND 44 VCM 43 SENSE 42 MODE 41 OF 40 D11 39 D10 38 OGND 37 OVDD
OVDD = VDD (Notes 1, 2)
Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... -0.3V to 1V Analog Input Voltage (Note 3) ..... -0.3V to (VDD + 0.3V) Digital Input Voltage .................... -0.3V to (VDD + 0.3V) Digital Output Voltage ............... -0.3V to (OVDD + 0.3V) Power Dissipation ............................................ 1500mW Operating Temperature Range LTC2224C ............................................... 0C to 70C LTC2224I .............................................-40C to 85C Storage Temperature Range ..................-65C to 125C
AIN+ 1 AIN- 2 REFHA 3 REFHA 4 REFLB 5 REFLB 6 REFHB 7 REFHB 8 REFLA 9 REFLA 10 VDD 11 VDD 12
49
36 D9 35 D8 34 D7 33 OVDD 32 OGND 31 D6 30 D5 29 D4 28 OVDD 27 OGND 26 D3 25 D2
UK PACKAGE 48-LEAD (7mm x 7mm) PLASTIC QFN EXPOSED PAD IS GND (PIN 49), MUST BE SOLDERED TO PCB TJMAX = 125C, JA = 29C/W
ORDER PART NUMBER LTC2224CUK LTC2224IUK
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
CO VERTER CHARACTERISTICS The denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25C. (Note 4)
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Integral Linearity Error Differential Linearity Error Offset Error Gain Error Offset Drift Full-Scale Drift Transition Noise Internal Reference External Reference SENSE = 1V Differential Analog Input (Note 5) Differential Analog Input Single-Ended Analog Input (Note 5) Single-Ended Analog Input (Note 6) External Reference

CONDITIONS

GND 13 VDD 14 GND 15 ENC + 16 ENC - 17 SHDN 18 OE 19 CLOCKOUT 20 DO 21 OGND 22 OVDD 23 D1 24
UK PART* MARKING LTC2224UK LTC2224UK
MIN 12 -1 -1
TYP 0.4 0.3 1 0.3
MAX 1 1
UNITS Bits LSB LSB LSB LSB
-35 -2.5
3 0.5 10 30 15 0.5
35 2.5
%FS V/C ppm/C ppm/C LSBRMS
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mV
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LTC2224
A ALOG I PUT
SYMBOL VIN VIN, CM IIN ISENSE IMODE tAP tJITTER CMRR
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
PARAMETER Analog Input Range (AIN+ - AIN-) Analog Input Common Mode (AIN+ Analog Input Leakage Current SENSE Input Leakage MODE Pin Pull-Down Current to GND Sample and Hold Acquisition Delay Time Sample and Hold Acquisition Delay Time Jitter Analog Input Common Mode Rejection Ratio Full Power Bandwidth Figure 8 Test Circuit + AIN-)/2 CONDITIONS 3.1V < VDD < 3.5V Differential Input Single Ended Input (Note 7) 0 < AIN+, AIN- < VDD 0V < SENSE < 1V

DY A IC ACCURACY
SYMBOL SNR PARAMETER Signal-to-Noise Ratio
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS. (Note 4)
CONDITIONS 30MHz Input (1V Range) 30MHz Input (2V Range) 70MHz Input (1V Range) 70MHz Input (2V Range) 140MHz Input (1V Range) 140MHz Input (2V Range) 250MHz Input (1V Range) 250MHz Input (2V Range) SFDR Spurious Free Dynamic Range 30MHz Input (1V Range) 30MHz Input (2V Range) 70MHz Input (1V Range) 70MHz Input (2V Range) 140MHz Input (1V Range) 140MHz Input (2V Range) 250MHz Input (1V Range) 250MHz Input (2V Range) SFDR Spurious Free Dynamic Range 4th Harmonic or Higher 30MHz Input (1V Range) 30MHz Input (2V Range) 70MHz Input (1V Range) 70MHz Input (2V Range) 140MHz Input (1V Range) 140MHz Input (2V Range) 250MHz Input (1V Range) 250MHz Input (2V Range) S/(N+D) Signal-to-Noise Plus Distortion Ratio 30MHz Input (1V Range) 30MHz Input (2V Range) 70MHz Input (1V Range) 70MHz Input (2V Range) IMD Intermodulation Distortion fIN1 = 138MHz, fIN2 = 140MHz

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MIN 1 0.5 -1 -1
TYP 0.5 to 1 1.6 1.6
MAX 1.9 2.1 1 1
UNITS V V V A A A ns psRMS dB MHz
10 0 0.15 80 775
MIN 66.5
TYP 62.8 67.6 62.8 67.6 62.5 67.3 61.8 65.9
MAX
UNITS dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dBc
72
84 84 84 84 84 84 77 77 90 90 90 90 90 90 90 90
66
62.8 67.4 62.8 67.2 81
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LTC2224
I TER AL REFERE CE CHARACTERISTICS
PARAMETER VCM Output Voltage VCM Output Tempco VCM Line Regulation VCM Output Resistance 3.1V < VDD < 3.5V -1mA < IOUT < 1mA CONDITIONS IOUT = 0
DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL VID VICM RIN CIN VIH VIL IIN CIN LOGIC OUTPUTS OVDD = 3.3V COZ ISOURCE ISINK VOH VOL OVDD = 2.5V VOH VOL OVDD = 1.8V VOH VOL High Level Output Voltage Low Level Output Voltage IO = -200A IO = 1.6mA High Level Output Voltage Low Level Output Voltage IO = -200A IO = 1.6mA Hi-Z Output Capacitance Output Source Current Output Sink Current High Level Output Voltage Low Level Output Voltage OE = High (Note 7) VOUT = 0V VOUT = 3.3V IO = -10A IO = -200A IO = 10A IO = 1.6mA PARAMETER Differential Input Voltage Common Mode Input Voltage Input Resistance Input Capacitance High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance (Note 7) VDD = 3.3V VDD = 3.3V VIN = 0V to VDD (Note 7) CONDITIONS ENCODE INPUTS (ENC +, ENC -)
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
MIN
LOGIC INPUTS (OE, SHDN)

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(Note 4)
MIN 1.575 TYP 1.600 25 3 4 MAX 1.625 UNITS V ppm/C mV/V
TYP
MAX
UNITS V
0.2 1.1 1.6 1.6 6 3 2 0.8 -10 3 10 2.5
Internally Set Externally Set (Note 7)
V V k pF V V A pF
3 50 50

pF mA mA V V 0.4 V V V V V V
3.1
3.295 3.29 0.005 0.09 2.49 0.09 1.79 0.09
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LTC2224
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 8)
SYMBOL VDD OVDD IVDD PDISS PSHDN PNAP PARAMETER Analog Supply Voltage Output Supply Voltage Analog Supply Current Power Dissipation Shutdown Power Nap Mode Power SHDN = High, OE = High, No CLK SHDN = High, OE = Low, No CLK CONDITIONS

POWER REQUIRE E TS
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
SYMBOL fS tL tH tAP tOE tD tC Pipeline Latency Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3.3V, OVDD = 1.8V, fSAMPLE = 135MHz, differential ENC+/ENC- = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. PARAMETER Sampling Frequency ENC Low Time ENC High Time Sample-and-Hold Aperture Delay Output Enable Delay ENC to DATA Delay ENC to CLOCKOUT Delay DATA to CLOCKOUT Skew (Note 7) (Note 7) (Note 7) (tC - tD) (Note 7)

TI I G CHARACTERISTICS
UW
MIN 3.1 0.5
TYP 3.3 3.3 191 630 2 35
MAX 3.5 3.6 206 680
UNITS V V mA mW mW mW
UW
CONDITIONS
MIN 1 3.5 2 3.5 2

TYP 3.7 3.7 3.7 3.7 0 5
MAX 135 500 500 500 500 10 3.5 3.5 0.6
UNITS MHz ns ns ns ns ns ns ns ns ns Cycles
Duty Cycle Stabilizer Off Duty Cycle Stabilizer On Duty Cycle Stabilizer Off Duty Cycle Stabilizer On
1.3 1.3 -0.6
2.1 2.1 0 5
Note 5: Integral nonlinearity is defined as the deviation of a code from a "best straight line" fit to the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from -0.5 LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2's complement output mode. Note 7: Guaranteed by design, not subject to test. Note 8: VDD = 3.3V, OVDD = 1.8V, fSAMPLE = 135MHz, differential ENC+/ENC- = 2VP-P sine wave, input range = 1VP-P with differential drive, output CLOAD = 5pF.
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LTC2224 TYPICAL PERFOR A CE CHARACTERISTICS
LTC2224: INL, 2V Range
1.0 0.8 0.6 0.4
ERROR (LSB) ERROR (LSB)
0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 OUTPUT CODE
2224 G01
0 -0.2 -0.4 -0.6 -0.8 -1.0
COUNT
0.2
3072
LTC2224: SNR vs Input Frequency, -1dB, 2V Range
69 67 65
SNR (dBFS)
63 61 59 57 55 0 100 400 500 INPUT FREQUENCY (MHz) 200 300 600
2224 G04
63 61 59 57 55 0 100 400 500 INPUT FREQUENCY (MHz) 200 300 600
2224 G05
SFDR (dBFS)
SNR (dBFS)
LTC2224: SFDR (HD2 and HD3) vs Input Frequency, -1dB, 1V Range
95 90 85
SFDR (dBFS) SFDR (dBFS)
75 70 65 60 55 50 0 100 400 500 INPUT FREQUENCY (MHz) 200 300 600
2224 G07
75 70 65 60 55 50 0 100 400 500 INPUT FREQUENCY (MHz) 200 300 600
2224 G08
SFDR (dBFS)
80
6
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LTC2224: DNL, 2V Range
1.0 0.8 0.6 0.4 0.2 60000 80000 100000
LTC2224: Shorted Input Noise Histogram
79331
40000 29529 21767 20000 123 2057 2058 2059 CODE
2224 G02 2224 G03
322 2060 2061
0 0 1024 2048 OUTPUT CODE 3072 4096
4096
LTC2224: SNR vs Input Frequency, -1dB, 1V Range
69 67 65 95 90 85 80 75 70 65 60 55 50
LTC2224: SFDR (HD2 and HD3) vs Input Frequency, -1dB, 2V Range
0
100
200 300 400 500 INPUT FREQUENCY (MHz)
600
2224 G06
LTC2224: SFDR (HD4+) vs Input Frequency, -1dB, 2V Range
95 90 85 80 95 90 85 80 75 70 65 60 55 50
LTC2224: SFDR (HD4+) vs Input Frequency, -1dB, 1V Range
0
100
200 300 400 500 INPUT FREQUENCY (MHz)
600
2224 G09
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LTC2224 TYPICAL PERFOR A CE CHARACTERISTICS
LTC2224: SFDR and SNR vs Sample Rate, 2V Range, fIN = 30MHz, -1dB
100 95
100 95
SFDR AND SNR (dBFS)
SFDR AND SNR (dBFS)
90 SFDR 85 80 75 70 65 60 SNR
IVDD (mA)
0
20
40
60 80 100 120 140 160 SAMPLE RATE (Msps)
2224 G10
LTC2224: IOVDD vs Sample Rate, 5MHz Sine Wave Input, -1dB, OVDD = 1.8V
20
100 90 80
SFDR (dBc AND dBFS)
IOVDD (mA)
10
0
0
20
UW
40
LTC2224: SFDR and SNR vs Sample Rate, 1V Range, fIN = 30MHz, -1dB
220 210 SFDR 200
LTC2224: IVDD vs Sample Rate, 5MHz Sine Wave Input, -1dB
90 85 80 75 70 65 60
2V RANGE
190
1V RANGE
180 170
SNR
160 150
0
20
40
60 80 100 120 140 160 SAMPLE RATE (Msps)
2224 G11
0
20
40
60 80 100 120 140 160 180 SAMPLE RATE (Msps)
2224 G12
LTC2224: SFDR vs Input Level, f IN = 70MHz, 2V Range
dBFS
70 60 50 40 30 20 10 dBc
60 80 100 120 140 160 180 SAMPLE RATE (Msps)
2224 G13
0 - 60
- 50
-30 -20 -40 INPUT LEVELS (dBFS)
-10
0
2224 G14
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LTC2224 TYPICAL PERFOR A CE CHARACTERISTICS
LTC2224: 8192 Point FFT, f IN = 30MHz, -1dB, 2V Range
0 - 10 - 20 - 30 0 - 10 - 20 - 30
AMPLITUDE (dB)
AMPLITUDE (dB)
- 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 FREQUENCY (MHz)
2224 G15
- 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 FREQUENCY (MHz)
2224 G16
AMPLITUDE (dB)
- 40
LTC2224: 8192 Point FFT, f IN = 70MHz, -1dB, 1V Range
0 - 10 - 20 - 30 0 - 10 - 20 - 30
AMPLITUDE (dB)
- 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 FREQUENCY (MHz)
2224 G18
- 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 FREQUENCY (MHz)
2224 G19
AMPLITUDE (dB)
- 40
AMPLITUDE (dB)
LTC2224: 8192 Point FFT, f IN = 250MHz, -1dB, 2V Range
0 - 10 - 20 - 30 0 - 10 - 20 - 30
AMPLITUDE (dB)
AMPLITUDE (dB)
- 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 FREQUENCY (MHz)
2224 G21
- 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 FREQUENCY (MHz)
2224 G22
AMPLITUDE (dB)
- 40
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LTC2224: 8192 Point FFT, f IN = 30MHz, -1dB, 1V Range
0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120
LTC2224: 8192 Point FFT, f IN = 70MHz, -1dB, 2V Range
- 40
0 5 10 15 20 25 30 35 40 45 50 55 60 65 FREQUENCY (MHz)
2224 G17
LTC2224: 8192 Point FFT, f IN = 140MHz, -1dB, 2V Range
0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120
LTC2224: 8192 Point FFT, f IN = 140MHz, -1dB, 1V Range
- 40
0 5 10 15 20 25 30 35 40 45 50 55 60 65 FREQUENCY (MHz)
2224 G20
LTC2224: 8192 Point FFT, f IN = 250MHz, -1dB, 1V Range
0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120
LTC2224: 8192 Point FFT, f IN = 500MHz, -6dB, 1V Range
- 40
0 5 10 15 20 25 30 35 40 45 50 55 60 65 FREQUENCY (MHz)
2224 G23
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LTC2224
PI FU CTIO S
AIN+ (Pin 1): Positive Differential Analog Input. AIN- (Pin 2): Negative Differential Analog Input. REFHA (Pins 3, 4): ADC High Reference. Bypass to Pins 5, 6 with 0.1F ceramic chip capacitor, to Pins 9, 10 with a 2.2F ceramic capacitor and to ground with a 1F ceramic capacitor. REFLB (Pins 5, 6): ADC Low Reference. Bypass to Pins 3, 4 with 0.1F ceramic chip capacitor. Do not connect to Pins 9, 10. REFHB (Pins 7, 8): ADC High Reference. Bypass to Pins 9, 10 with 0.1F ceramic chip capacitor. Do not connect to Pins 3, 4. REFLA (Pins 9, 10): ADC Low Reference. Bypass to Pins 7, 8 with 0.1F ceramic chip capacitor, to Pins 3, 4 with a 2.2F ceramic capacitor and to ground with a 1F ceramic capacitor. VDD (Pins 11, 12, 14, 46, 47): 3.3V Supply. Bypass to GND with 0.1F ceramic chip capacitors. Adjacent pins can share a bypass capacitor. GND (Pins 13, 15, 45, 48): ADC Power Ground. ENC + (Pin 16): Encode Input. The input is sampled on the positive edge. ENC - (Pin 17): Encode Complement Input. The input is sampled on the negative edge. Bypass to ground with 0.1F ceramic for single-ended ENCODE signal. SHDN (Pin 18): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance. OE (Pin 19): Output Enable Pin. Refer to SHDN pin function. CLOCKOUT (Pin 20): Data Valid Output. Latch data on the falling edge of CLOCKOUT. D0 - D11 (Pins 21, 24, 25, 26, 29, 30, 31, 34, 35, 36, 39, 40): Digital Outputs. D11 is the MSB. OGND (Pins 22, 27, 32, 38): Output Driver Ground. OVDD (Pins 23, 28, 33, 37): Positive Supply for the Output Drivers. Bypass to ground with 0.1F ceramic chip capacitors. OF (Pin 41): Over/Under Flow Output. High when an over or under flow has occurred. MODE (Pin 42): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and turns the clock duty cycle stabilizer off. Connecting MODE to 1/3 VDD selects offset binary output format and turns the clock duty cycle stabilizer on. Connecting MODE to 2/3 VDD selects 2's complement output format and turns the clock duty cycle stabilizer on. Connecting MODE to VDD selects 2's complement output format and turns the clock duty cycle stabilizer off. SENSE (Pin 43): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a 0.5V input range. VDD selects the internal reference and a 1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of VSENSE. 1V is the largest valid input range. VCM (Pin 44): 1.6V Output and Input Common Mode Bias. Bypass to ground with 2.2F ceramic chip capacitor. Exposed Pad (Pin 49): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground.
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LTC2224
FUNCTIONAL BLOCK DIAGRA
AIN+ INPUT S/H FIRST PIPELINED ADC STAGE
AIN-
SECOND PIPELINED ADC STAGE
VCM 2.2F
1.6V REFERENCE SHIFT REGISTER AND CORRECTION
RANGE SELECT
REFH SENSE REF BUF
DIFF REF AMP
REFLB REFHA 2.2F 0.1F 1F
Figure 1. Functional Block Diagram
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THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE REFL INTERNAL CLOCK SIGNALS OVDD OF DIFFERENTIAL INPUT LOW JITTER CLOCK DRIVER CONTROL LOGIC OUTPUT DRIVERS * * * D11 D0 CLOCKOUT REFLA REFHB ENC 0.1F 1F
+
2224 F01
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OGND ENC
-
M0DE
SHDN
OE
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LTC2224
TI I G DIAGRA S
Timing Diagram
tAP ANALOG INPUT N tH tL ENC - ENC + tD D0-D11, OF tC N-5 N-4 N-3 N-2 N-1 N+1 N+2 N+3 N+4
CLOCKOUT
OE t OE DATA OF, D0-D11, CLOCKOUT t OE
W
UW
2224 TD01
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LTC2224
APPLICATIO S I FOR ATIO
DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20Log ((V22 + V32 + V42 + . . . Vn2)/V1) where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency.
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If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa - fb and 2fb - fa. The intermodulation distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product. Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. Full Power Bandwidth The full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Aperture Delay Time The time from when a rising ENC+ equals the ENC- voltage to the instant that the input signal is held by the sample and hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = -20log (2 * fIN * tJITTER)
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LTC2224
APPLICATIO S I FOR ATIO
CONVERTER OPERATION As shown in Figure 1, the LTC2224 is a CMOS pipelined multistep converter. The converter has five pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially. For cost sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The encode input is differential for improved common mode noise immunity. The LTC2224 has two phases of operation, determined by the state of the differential ENC+/ENC- input pins. For brevity, the text will refer to ENC+ greater than ENC- as ENC high and ENC+ less than ENC- as ENC low. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When ENC is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the "Input S/H" shown in the block diagram. At the instant that ENC transitions from low to high, the sampled input is held. While ENC is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of ENC. When ENC goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When ENC goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third and fourth stages, resulting in a fourth
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stage residue that is sent to the fifth stage ADC for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2224 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input.
LTC2224 VDD 15 CPARASITIC 1pF CSAMPLE 1.6pF CPARASITIC 1pF VDD CSAMPLE 1.6pF AIN+ VDD 15 AIN- 1.6V 6k ENC+ ENC- 6k 1.6V
2224 F02
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Figure 2. Equivalent Input Circuit
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LTC2224
APPLICATIO S I FOR ATIO
During the sample phase when ENC is low, the transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. When ENC transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when ENC is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As ENC transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Single-Ended Input For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and DNL will remain unchanged. For a single-ended input, AIN+ should be driven with the input signal and AIN- should be connected to 1.6V or VCM. Common Mode Bias For optimal performance the analog inputs should be driven differentially. Each input should swing 0.5V for the 2V range or 0.25V for the 1V range, around a common mode voltage of 1.6V. The VCM output pin (Pin 44) may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2F or greater capacitor.
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Input Drive Impedance As with all high performance, high speed ADCs, the dynamic performance of the LTC2224 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can influence SFDR. At the falling edge of ENC, the sampleand-hold circuit will connect the 1.6pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when ENC rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance, it is recommended to have a source impedance of 100 or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits Figure 3 shows the LTC2224 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input
VCM 2.2F 0.1F ANALOG INPUT T1 1:1 25 25 25 0.1F 12pF 25 AIN-
2224 F03
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AIN+
LTC2224
T1 = MA/COM ETC1-1T RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 3. Single-Ended to Differential Conversion Using a Transformer
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LTC2224
APPLICATIO S I FOR ATIO
signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100 for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input frequencies. Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This circuit is not recommended if low distortion is required. The 25 resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. For input frequencies higher than 100MHz, the capacitor may need to be decreased to prevent excessive signal loss.
VCM HIGH SPEED DIFFERENTIAL AMPLIFIER 25 ANALOG INPUT 2.2F AIN+
0.1F 1k 1k 25
LTC2224
+
CM
+ -
3pF 12pF 25 3pF AIN-
2224 F04
-
LTC6600-20 OR LT1993
Figure 4. Differential Drive with an Amplifier
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For input frequencies above 100MHz the input circuits of Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.6V. In Figure 8 the series inductors are impedance matching elements that maximize the ADC bandwidth. Reference Operation Figure 9 shows the LTC2224 reference circuitry consisting of a 1.6V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (1V differential) or 1V (0.5V differential). Tying the SENSE pin to VDD selects the 2V range; typing the SENSE pin to VCM selects the 1V range. The 1.6V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.6V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry.
VCM 2.2F AIN+ LTC2224 ANALOG INPUT 12pF 25 0.1F AIN-
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Figure 5. Single-Ended Drive
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LTC2224
APPLICATIO S I FOR ATIO
VCM 2.2F 0.1F ANALOG INPUT 25 T1 0.1F 25 12 AIN- T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 12 0.1F 8pF AIN+
LTC2224
Figure 6. Recommended Front End Circuit for Input Frequencies Between 100MHz and 250MHz
VCM 2.2F 0.1F ANALOG INPUT 25 T1 0.1F 25 AIN- T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
2224 F07
AIN+ 0.1F
LTC2224
Figure 7. Recommended Front End Circuit for Input Frequencies Between 250MHz and 500MHz
VCM
2.2F
2.2F 0.1F ANALOG INPUT 25 T1 0.1F 25 4.7nH AIN- T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS, INDUCTORS ARE 0402 PACKAGE SIZE
2224 F08
4.7nH 0.1F
AIN+
LTC2224
2pF
Figure 8. Recommended Front End Circuit for Input Frequencies Above 500MHz
The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has four pins: two each of REFHA and REFHB for the high reference and two each of REFLA
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and REFLB for the low reference. The multiple output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9. Other voltage ranges in between the pin selectable ranges can be programmed with two external resistors as shown in Figure 10. An external reference can be used by applying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1F ceramic capacitor.
LTC2224 1.6V VCM 2.2F 1V RANGE DETECT AND CONTROL SENSE REFLB 0.1F REFHA BUFFER INTERNAL ADC HIGH REFERENCE 0.5V 4 1.6V BANDGAP REFERENCE
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TIE TO VDD FOR 2V RANGE; TIE TO VCM FOR 1V RANGE; RANGE = 2 * VSENSE FOR 0.5V < VSENSE < 1V 1F
DIFF AMP 1F REFLA 0.1F REFHB INTERNAL ADC LOW REFERENCE
2224 F09
Figure 9. Equivalent Reference Circuit
1.6V
VCM 2.2F
12k 0.8V 12k SENSE 1F LTC2224
2224 F10
Figure 10. 1.6V Range ADC
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LTC2224
APPLICATIO S I FOR ATIO
Input Range
The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 5dB. See the Typical Performance Characteristics section. Driving the Encode Inputs The noise performance of the LTC2224 can depend on the encode signal quality as much as on the analog input. The ENC+/ENC- inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 6k resistor to a 1.6V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical (high input frequencies) take the following into consideration:
LTC2224 VDD
TO INTERNAL ADC CIRCUITS 1.6V BIAS 6k ENC+ 0.1F CLOCK INPUT 50 1:4 VDD 1.6V BIAS 6k ENC-
VDD
Figure 11. Transformer Driven ENC+/ENC-
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1. Differential drive should be used. 2. Use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase the amplitude. 3. If the ADC is clocked with a sinusoidal signal, filter the encode signal to reduce wideband noise. 4. Balance the capacitance and series resistance at both encode inputs so that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.1V to 2.5V. Each input may be driven from ground to VDD for single-ended drive. Maximum and Minimum Encode Rates The maximum encode rate for the LTC2224 is 135Msps. For the ADC to operate properly, the encode signal should have a 50% (5%) duty cycle. Each half cycle must have at least 3.5ns for the ADC internal circuitry to have enough settling time for proper operation. Achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS. An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the ENC+ pin to sample the analog input. The falling edge of ENC+ is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 30% to 70% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors. The lower limit of the LTC2224 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2224 is 1Msps.
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LTC2224
APPLICATIO S I FOR ATIO
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input voltage, the digital data bits and the overflow bit.
Table 1. Output Codes vs Input Voltage
AIN+ - AIN- (2V Range) >+1.000000V +0.999512V +0.999024V +0.000488V 0.000000V -0.000488V -0.000976V -0.999512V -1.000000V <-1.000000V OF 1 0 0 0 0 0 0 0 0 1 D11 - D0 (Offset Binary) 1111 1111 1111 1111 1111 1111 1111 1111 1110 1000 0000 0001 1000 0000 0000 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 0000 0000 0000 D11 - D0 (2's Complement) 0111 1111 1111 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 1000 0000 0001 1000 0000 0000 1000 0000 0000
Digital Output Buffers Figure 13 shows an equivalent circuit for a single output buffer. Each buffer is powered by OVDD and OGND, which are isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to voltages as low as 0.5V. The internal resistor in series with the output makes the output appear as 50 to external circuitry and may eliminate the need for external damping resistors.
VTHRESHOLD = 1.6V ENC+
1.6V ENC- 0.1F
LTC2224
VDD
VDD
2224 F12a
Figure 12a. Single-Ended ENC Drive, Not Recommended for Low Jitter
3.3V MC100LVELT22 3.3V 130 Q0 130
D0
ENC+ ENC- 83 83
2224 F12b
LTC2224
Q0
Figure 12b. ENC Drive Using a CMOS to PECL Translator
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As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2224 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. For full speed operation the capacitive load should be kept under 5pF. Lower OVDD voltages will also help reduce interference from the digital outputs and improve the SNR. Data Format The LTC2224 parallel digital output can be selected for offset binary or 2's complement format. The format is selected with the MODE pin. Connecting MODE to GND or 1/3VDD selects offset binary output format. Connecting MODE to 2/3VDD or VDD selects 2's complement output format. An external resistor divider can be used to set the 1/3VDD or 2/3VDD logic values. Table 2 shows the logic states for the MODE pin.
Table 2. MODE Pin Function
MODE Pin 0 1/3VDD 2/3VDD VDD Output Format Offset Binary Offset Binary 2's Complement 2's Complement Clock Duty Cycle Stablizer Off On On Off
LTC2224
OVDD 0.5V TO 3.6V
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0.1F
OVDD
DATA FROM LATCH
OE
PREDRIVER LOGIC
43
TYPICAL DATA OUTPUT OGND
2224 F13
Figure 13. Digital Output Buffer
LTC2224
APPLICATIO S I FOR ATIO
Overflow Bit
The converter is either overranged or underranged when OF outputs a logic high. Output Clock The ADC has a delayed version of the ENC+ input available as a digital output, CLOCKOUT. The CLOCKOUT pin can be used to synchronize the converter data to the digital system. This is necessary when using a sinusoidal encode. Data will be updated just after CLOCKOUT rises and can be latched on the falling edge of CLOCKOUT. Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example if the converter is driving a DSP powered by a 1.8V supply then OVDD should be tied to that same 1.8V supply. OVDD can be powered with any voltage up to 3.6V. OGND can be powered with any voltage from GND up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD. Output Enable The outputs may be disabled with the output enable pin, OE. OE high disables all data outputs including OF and CLOCKOUT. The data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed operation. The output Hi-Z state is intended for use during long periods of inactivity. Sleep and Nap Modes The converter may be placed in shutdown or nap modes to conserve power. Connecting SHDN to GND results in normal operation. Connecting SHDN to VDD and OE to VDD results in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mW. When exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. Connecting SHDN to VDD and OE
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to GND results in nap mode, which typically dissipates 35mW. In nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. In both sleep and nap mode all digital outputs are disabled and enter the Hi-Z state. GROUNDING AND BYPASSING The LTC2224 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital signal alongside an analog signal or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, OVDD, VCM, REFHA, REFHB, REFLA and REFLB pins as shown in the block diagram on the front page of this data sheet. Bypass capacitors must be located as close to the pins as possible. Of particular importance are the capacitors between REFHA and REFLB and between REFHB and REFLA. These capacitors should be as close to the device as possible (1.5mm or less). Size 0402 ceramic capacitors are recommended. The 2.2F capacitor between REFHA and REFLA can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC2224 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. HEAT TRANSFER Most of the heat generated by the LTC2224 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad should be soldered to a large grounded pad on the PC board. It is critical that all ground pins are connected to a ground plane of sufficient area.
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LTC2224
APPLICATIO S I FOR ATIO
Clock Sources for Undersampling
Undersampling raises the bar on the clock source and the higher the input frequency, the greater the sensitivity to clock jitter or phase noise. A clock source that degrades SNR of a full-scale signal by 1dB at 70MHz will degrade SNR by 3dB at 140MHz, and 4.5dB at 190MHz. In cases where absolute clock frequency accuracy is relatively unimportant and only a single ADC is required, a 3V canned oscillator from vendors such as Saronix or Vectron can be placed close to the ADC and simply connected directly to the ADC. If there is any distance to the ADC, some source termination to reduce ringing that may occur even over a fraction of an inch is advisable. You must not allow the clock to overshoot the supplies or performance will suffer. Do not filter the clock signal with a narrow band filter unless you have a sinusoidal clock source, as the rise and fall time artifacts present in typical digital clock signals will be translated into phase noise. The lowest phase noise oscillators have single-ended sinusoidal outputs, and for these devices the use of a filter close to the ADC may be beneficial. This filter should be close to the ADC to both reduce roundtrip reflection times, as well as reduce the susceptibility of the traces between the filter and the ADC. If you are sensitive to close-in phase noise, the power supply for oscillators and any buffers
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must be very stable, or propagation delay variation with supply will translate into phase noise. Even though these clock sources may be regarded as digital devices, do not operate them on a digital supply. If your clock is also used to drive digital devices such as an FPGA, you should locate the oscillator, and any clock fan-out devices close to the ADC, and give the routing to the ADC precedence. The clock signals to the FPGA should have series termination at the source to prevent high frequency noise from the FPGA disturbing the substrate of the clock fan-out device. If you use an FPGA as a programmable divider, you must re-time the signal using the original oscillator, and the retiming flip-flop as well as the oscillator should be close to the ADC, and powered with a very quiet supply. For cases where there are multiple ADCs, or where the clock source originates some distance away, differential clock distribution is advisable. This is advisable both from the perspective of EMI, but also to avoid receiving noise from digital sources both radiated, as well as propagated in the waveguides that exist between the layers of multilayer PCBs. The differential pairs must be close together, and distanced from other signals. The differential pair should be guarded on both sides with copper distanced at least 3x the distance between the traces, and grounded with vias no more than 1/4 inch apart.
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LTC2224
APPLICATIO S I FOR ATIO U
VCC CLOCKOUT JP1 VCC CLOCKOUT
R19 OPT ANALOG INPUT J1
C1 0.1F
R1* T1* R2 24.9 C2* R4 24.9
C3 0.1F VCM R5 50 C4 0.1F
R6* 1 2 3 4 13 C5 1F C6 0.1F 15 5
C7 2.2F
6 7 8 C8 1F C9 0.1F 9 10
VDD
VDD
46 47 11 12 14 CLK SHDN C11 33pF CLK 16 17 18 19 44 C15 2.2F 43 42
C10 0.1F C12 0.1F
VDD JP2 GND C13 0.1F
JP3 SENSE VDD VDD VCM VCM EXT REF EXT REF R13 1k R14 1k C22 0.1F VCC R12 1k VDD
JP4 MODE VDD
2/3VDD
1/3VDD C24 0.1F C20 0.1F
GND
C27 10F 6.3V
R17 105k R18 100k C28 0.01F
U6 LT1763 1 8 OUT IN 2 7 ADJ GND 3 6 GND GND 4 5 BYP SHDN
VDD ENCODE INPUT
C34 1F
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Evaluation Circuit Schematic of the LTC2224
34 45
VCC
GND GND GND VCC 2LE 1LE 2OE 1OE 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8
U3
GND VCC GND GND VCC GND GND VCC 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2Q1 2Q2 2Q3
28 31 21 15 18 10 4 7 2 3 5 6 8 9 11 12 13 14 16 17
RN1D 33 RN1C 33 RN1B 33 RN1A 33 RN2D 33 RN2C 33 RN2B 33 RN2A 33 RN3D 33 RN3C 33 RN3B 33 RN3A 33 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 C33 0.1F 1 2 5 NC7SV86P5X 4 R3 33
39 42 25 48 24 1 47
U2
3
39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3
C17 0.1F
40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
3201S-40G1
U1 LTC2224* 20 AIN+ CLOCKOUT 21 AIN- D0 24 REFHA D1 25 REFHA D2 26 GND D3 29 GND D4 30 REFLB D5 31 REFLB D6 34 REFHB D7 35 REFHB D8 36 REFLA D9 39 REFLA D10 40 VDD D11 41 VDD OF 37 VDD OVDD 33 VDD OVDD 28 VDD OVDD 23 + ENC OVDD 38 ENC- OGND 32 SHDN OGND 27 OE OGND 22 VCM OGND 48 SENSE GND 45 MODE GND GND 49
46 44 43 41 40 38 37 36 35 33 32 30 29 27 26
2Q4
19
2Q5
20
2Q6 2Q7 2Q8
22 23
PI74VCX16373A VCC NC7SV86P5X 4 5 U5 3 1 2 C16 0.1F
1
R10 10k R9 10k R8 10k
1 8 A0 U4 VCC 2 7 A1 WP 3 6 A2 SCL 4 5 A3 SDA 24LC025
2224 AI01
VDD GND C25 4.7F PWR GND VDD 3.3V
VCC C29 0.1F C30 0.1F C31 0.1F C32 0.1F
C21 0.1F
Assembly Type DC751A-I
VCC
U1 LTC2224CUK LTC2234CUK LTC2224CUK LTC2234CUK
R1, R6 24.9 24.9 12.4 12.4
C2 12pF 12pF 8.2pF 8.2pF
T1 ETC1-1T ETC1-1T ETC1-1-13 ETC1-1-13
C19 0.1F
DC751A-J DC751A-K DC751A-L
CLK
C18 0.1F C23 J3 0.1F R16 100 T2 ETC1-1T
*Version Type
R15 100 CLK C26 0.1F
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LTC2224
APPLICATIO S I FOR ATIO
Layer 1 Component Side
Layer 3 Power Plane
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Silkscreen Top Layer 2 GND Plane Layer 4 Bottom Side
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LTC2224
PACKAGE DESCRIPTIO
0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 7.00 0.10 (4 SIDES) 0.75 0.05 R = 0.115 TYP
PIN 1 TOP MARK (SEE NOTE 6) PIN 1 CHAMFER
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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UK Package 48-Lead Plastic QFN (7mm x 7mm)
(Reference LTC DWG # 05-08-1704)
0.70 0.05 5.15 0.05 6.10 0.05 7.50 0.05 (4 SIDES) NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PACKAGE OUTLINE 47 48 0.40 0.10 1 2 5.15 0.10 (4-SIDES) 0.200 REF 0.00 - 0.05 0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD
(UK48) QFN 1103
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LTC2224
RELATED PARTS
PART NUMBER LTC1748 LTC1750 LT1993-2 LT1994 LTC2202 LTC2208 LTC2220-1 LTC2222 LTC2222-11 LTC2223 LTC2224 LTC2232 LTC2233 LTC2234 LTC2255 LTC2284 LT5512 LT5514 LT5515 LT5516 LT5517 LT5522 DESCRIPTION 14-Bit, 80Msps, 5V ADC 14-Bit, 80Msps, 5V Wideband ADC High Speed Differential Op Amp Low Noise, Low Distortion Fully Differential Input/Output Amplifier/Driver 16-Bit, 10Msps, 3.3V ADC, Lowest Noise 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs 12-Bit, 185Msps, 3.3V ADC, LVDS Outputs 12-Bit, 105Msps, 3.3V ADC, High IF Sampling 11-Bit, 105Msps, 3.3V ADC, High IF Sampling 12-Bit, 80Msps, 3.3V ADC, High IF Sampling 12-Bit, 135Msps, 3.3V ADC, High IF Sampling 10-Bit, 105Msps, 3.3V ADC, High IF Sampling 10-Bit, 80Msps, 3.3V ADC, High IF Sampling 10-Bit, 135Msps, 3.3V ADC, High IF Sampling 14-Bit, 125Msps, 3V ADC, Lowest Power 14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk DC-3GHz High Signal Level Downconverting Mixer Ultralow Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain 1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator 800MHz to 1.5GHz Direct Conversion Quadrature Demodulator 40MHz to 900MHz Direct Conversion Quadrature Demodulator 600MHz to 2.7GHz High Linearity Downconverting Mixer COMMENTS 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package Up to 500MHz IF Undersampling, 90dB SFDR 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain Low Distortion: -94dBc at 1MHz 150mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN 1250mW, 78dB SNR, 100dB SFDR, 64-Pin QFN 910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN 475mW, 68.4dB SNR, 84dB SFDR, 48-Pin QFN 475mW, 65.7dB SNR, 84dB SFDR, 48-Pin QFN 366mW, 68.5dB SNR, 84dB SFDR, 48-Pin QFN 630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN 475mW, 61.3dB SNR, 78dB SFDR, 48-Pin QFN 366mW, 61.3dB SNR, 78dB SFDR, 48-Pin QFN 630mW, 61.2dB SNR, 78dB SFDR, 48-Pin QFN 395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN 540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN DC to 3GHz, 21dBm IIP3, Integrated LO Buffer 450MHz 1dB BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 500 Single-Ended RF and LO Ports
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
LT 0106 REV A * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2004

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